Boundary Element Method Macromodels for 2-D Hierarchical Capacitance Extraction†
نویسندگان
چکیده
A 2-D hierarchical field solution method was recently introduced for capacitance extraction for VLSI interconnect modeling. In this paper, we present several extensions to the method including a Boundary Element Method (BEM) formulation for creating macromodels, which provides a better trade-off between accuracy and efficiency, as well as parameterized elements, which allow the analysis of gridless designs with reasonable accuracy and a small library size.
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